Technical Field
The present invention relates to measuring duty cycle of a signal and, more particularly, to finding the width of a signal in proportion to the period of the signal.
Description of the Related Art
There is often a need to measure the duty cycle of clock signals on integrated chips. This measurement makes it possible to maintain the duty cycle at some optimal value (e.g., 50%). The duty cycle is defined as the ratio of the width of a signal (e.g., in a digital signal when the signal level is ‘high’) to the period of the signal.
There are three conventional types of duty cycle measurement. In analog measurement, capacitors are charged, usually with true and complement signals, and the average DC value is measured to give the ratio of on-time to the period. However, analog measurement necessitates off-chip voltage measurement or on-chip analog-to-digital conversion, which involves significant additional care in the chip design and elaborate calibration. In asynchronous sampling, an asynchronous clock samples a clock of interest and counters store the result, from which an on/off ratio is determined. However, asynchronous sampling uses very large counters to provide adequate precision. In a latched delay chain, the chains samples an entire waveform using a large number of latches to form a time-to-digital converter. This provides a multi-bit code describing the pulse width, from which the duty cycle can be computed, but at the cost of being very complex, using a large amount of surface area, and necessitating off-chip analysis of the collected data.